1. Field of the Invention
The present invention relates to the field of serial peripheral interface devices.
2. Related Art
The serial peripheral interface (hereinafter referred to as “SPI”) bus can provide a synchronous serial data connection between SPI devices and/or microprocessors. One particular usage of the SPI bus includes a single chip microprocessor with limited non-volatile memory but with internal random access memory for program storage. The microprocessor is connected to an electrically-erasable programmable read-only memories (hereinafter referred to as “EEPROMs”) via an SPI bus. Upon booting up the device containing the microprocessor chip, the EEPROM can transfer its non-volatile information to the microprocessor in order to program the device for use in a universal serial bus (hereinafter referred to as “USB”) communication system.
However, before reading the EEPROM, the address counter in the EEPROM must be set to a certain address in order to access the information stored on the EEPROM correctly. The memory controller sends out a “READ” command which starts at a certain address, cleared to zero in most cases. Thus, the memory controller must recognize what size of EEPROM is attached in order to send out the correct start address. Depending on the size of the EEPROM, the address may be one, two, three bytes, or larger.
Electrically-erasable programmable read-only memories are available with a variety of serial bus interfaces. For example, Microchip, Atmel, ST Microelectronics, Catalyst Semiconductor and other manufacturers offer EEPROM devices in various densities and interfaces. Such interfaces are typically characterized as “2-wire” or “3-wire”. The SPI (Serial Peripheral Interface) bus is a “3-wire” interface, utilizing a data in terminal, a data out terminal, and a serial clock terminal. A fourth “chip select” terminal is required to activate the device, making SPI actually a “4-wire” interface. The SPI bus offers advantages over other serial interfaces such as a higher rate of data transfer. Additionally, the SPI bus offers a more secure memory-write mechanism that has better noise immunity to false writes than other communication buses.
SPI EEPROMs are offered in various densities of memory. For example the Atmel AT25010 is 1 Kilobit, organized 128×8, and the Atmel AT25640 is 64 Kilobits, organized 8K×8. For example, in systems that support the above two sizes of EEPROMs, a fifth “size” or mode pin is required to allow the memory controller to recognize what size of EEPROM is connected. Once the correct size of SPI device is recognized, the memory controller can generate the correct series of signals for each of the two above memory sizes in order to coordinate the flow of information to and from the SPI device. For an SPI bus, this makes the total interface a “5-pin” interface.
A particular problem with using a mode pin involves human error. Since the mode pin is a user settable switch, the mode pin could be jumpered or set incorrectly. In this case, the memory controller would send out the incorrect signal to the EEPROM and at the very least not allow the EEPROM to transfer useable information to the microprocessor. The USB device containing the microprocessor thus would not be enabled.
Moreover, pin usage on the microprocessor is at a premium. It is desirable in systems that use SPI EEPROMs to conserve the number of interface pins used to read and write the EEPROM.
Thus, it would be advantageous to provide a more reliable way to coordinate the flow of information in and out of serial SPI devices. Also, it would be advantageous to provide a way to conserve the number of interface pins used to coordinate the flow of information in and out SPI devices.